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industrial current/voltage output driver with programmable ranges data sheet ad5750 / ad5750 - 1 / ad5750 - 2 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is g ranted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 C 2012 analog devices, inc. all rights reserved. features current output ranges: 4 ma to 20 ma, 0 ma to 20 ma , 0 ma to 24 ma, 20 ma, and 24 ma 0.03% full - scale range ( fsr ) total unadjusted error (tue) 5 ppm/ c typical output drift voltage output ranges: 0 v to 5 v, 0 v to 10 v, 5 v, and 10 v with 20% overrange 0.02% fsr tue 3 ppm/ c typical output drift flexible serial digital interface on - chip output fault detection p acket error checking (pec) asynchronous clear functio n flexible power - up condition to 0 v or tristate power supply range av dd : +12 v ( 10%) to +24 v ( 10%) av ss : ? 12 v ( 10%) to ?24 v ( 10%) output loop compliance to av dd ? 2.75 v temperature range: ? 40c to +105c 32- lead , 5 mm 5 mm lfcsp package applications process control s actuator control s plcs general description the ad5750 / ad5750 - 1 / ad5750 - 2 are sing le - channel, low cost, precision voltage/current output driver s with hardware - or software - programmable output ranges. the software ranges are configured via an spi - /microwire? - compatible serial interface. the ad 5750/ ad5750 - 1 / ad5750 - 2 target applications in plc and industrial process control. the analog input to the ad5750 / ad5750 - 1 / ad5750 - 2 is provided from a low voltage, single - supply digital - to - analog converter (dac) and is internally conditioned to provide the desired output curren t/voltage range. analog input ranges available are 0 v to 2.5 v ( ad5750 - 1 / ad5750 - 2 ) or 0 v to 4.096 v ( ad5750 ). the output current range is programmable across five current ranges: 4 ma to 20 ma, 0 ma to 20 ma , 0 ma to 24 ma, 20 ma, and 24 ma. an overrange of 2% is available on the unipolar current ranges. voltage output is provided from a separate pin that can be configured to provide 0 v to 5 v, 0 v to 10 v, 5 v, or 10 v output ranges. an overrange of 20% is available on the voltage ranges. analog outputs are short - circuit and open - circuit protected and can drive capacitive loads of 1 f and inductive loads of 0.1 h. the device s are specified to operate with a power supply range from 12 v to 24 v. output loop compliance is 0 v to av dd ? 2.75 v. the flexible serial interface is spi and microwire compa tible and can operate in 3 - wire mode to minimize the digital isolation required in isolated applications. the interface also features an optional pec feature using crc - 8 error checking, useful in industrial environments where data communication corruption can occur. the device s also include a power - on - reset function , ensuring that the device s power up in a known state (0 v or tristate), and an asynchronous clear pin that sets the outputs to a zero scale/mid - scale voltage output or the low end of the selected current range. the hw select pin is used to configure the part s for hardware or software mode on power - u p. table 1 . related device s part number description ad5422 single channel, 16 - bit, serial input current source and voltage output dac ad5751 industrial i/v output driver, single supply, 55 v maximum supply, programmable ranges ad5420 single channel, 16 - bit, serial input, 4 ma to 20 ma current source dac
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 timing characteristics ................................................................ 8 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 voltage output ............................................................................ 13 current output ........................................................................... 17 terminology .................................................................................... 22 theory of operat ion ...................................................................... 23 software mode ............................................................................ 23 current output architecture .................................................... 25 driving inductive loads ............................................................ 25 power - on state of ad5750/ad5750 - 1/ad5750 - 2 ................... 25 default registers at power - on ................................................. 26 reset function ............................................................................ 26 outen ........................................................................................ 26 software control ........................................................................ 26 hardware control ...................................................................... 28 transfer function ....................................................................... 28 detailed description of features .................................................. 29 output fault alert software mode ....................................... 29 output fault alert hardware mode ..................................... 29 voltage output short - circuit protection ................................ 29 asynchronous clear (clear) ................................................. 29 external current setting resistor ............................................ 30 programmable overrange modes ............................................ 30 packet error checking ............................................................... 30 applications information .............................................................. 31 transient voltage protection .................................................... 31 thermal considerations ............................................................ 31 layout guidelines ....................................................................... 3 1 galvanically isolated interface ................................................. 32 microprocessor interfacing ....................................................... 32 ou tline dimensions ....................................................................... 33 ordering guide .......................................................................... 33 revision history 6/12 rev. d to rev. e changes to figure 3 .......................................................................... 9 changes to status bit read operation section ........................... 28 updated outline dimensions ....................................................... 33 4 /12 rev. c to rev. d added ad5750 - 2 ................................................................ universal changes to table 2 ............................................................................ 4 updated outline dimensions ....................................................... 33 changes to ordering guide .......................................................... 33 7/10 rev. b to rev. c added leakage current in voltage output characteristics parameter (table 2) .......................................................................... 5 added leakage current in current output characteristics parameter (table 2) .......................................................................... 6 6/10 rev . a to rev. b changes to table 1 ............................................................................ 1 changes to table 2, power requirements ..................................... 7 8/09 rev. 0 to rev. a added ad5750 - 1 ................................................................ universal changes to features and general description sections .............. 1 changes to table 2 ............................................................................. 4 changes to theory of operation section and figure 51 .......... 23 change to figure 52 and table 6 title ......................................... 24 changes to current output architecture section and power - on state of ad5750/ad5750 - 1 .......................................................... 25 changes to transfer function section ........................................ 28 changes to programmable overrange modes section ............. 30 changes to ordering guide .......................................................... 33 7/09 revision 0: initial version
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 3 of 36 functional block dia gram figure 1. clear vsense+ vout vsense? rext1 iout dv cc gnd a v dd gnd comp1 comp2 ad2/ r1 * ad1/ r2 * ad0/ r3 * a v ss clrse l hw select vin vref sclk/ outen * sdin/ r0 * sync/ rset * sdo/ vf au l t * input shift register and contro l logic sta tus register vout range scaling iout range scaling vout short f au l t power- on reset f au l t/ tem p* nc/ if au l t * overtem p vout short f au l t iout open f au l t reset r set vx** v ss v dd r2 r3 rext2 iout open f au l t ad5750/ad5750-1/AD5750-2 * denotes shared pin. soft w are mode denoted b y regular tex t , hard w are mode denoted b y it alic tex t . for example, for f au l t/ tem p pin, in soft w are mode, this pin t akes on f au l t function. in hard w are mode, this pin t akes on tem p function. ** vx is an interna l bias vo lt age (can be ground or other vo lt age) th a t is used t o gener a te the interna l sense currents needed for the current outputs. 07268-001
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 4 of 36 specifications av dd /av ss = 12 v ( 10%) to 24 v ( 10%) , dv cc = 2.7 v to 5.5 v, gnd = 0 v. i out : r load = 300 ?. all specifications t min to t max , unless otherwise noted. table 2 . parameter 1 min typ max unit test conditions/comments input voltage range output unloaded 0 to 4.096 v ad5750 0 to 2.5 ad5750 -1 / ad5750 -2 input leakage current ? 1 + 1 a reference input reference input voltage 4.096 v ad5750 ; e xternal reference must to be exactly as stated; otherwise, accuracy errors show up as error in output 2.5 v ad5750 -2 ; external reference needs to be exactly as stated; otherwise, accuracy errors show up as error in output 1.25 v ad5750 -1 ; external reference needs to be exactly as stated; otherwise, accuracy errors show up as error in output input leakage current ? 1 + 1 a voltage output output voltage ranges 0 5 v 0 10 v av dd needs to have minimum 1 .3 v headroom or >11. 3 v ?5 +5 v ?10 +10 v av dd /av ss needs to have minimum 1. 3 v headroom or >11. 3 v output voltage overranges 0 6 v programmable overranges; see the detailed description of features section 0 12 v ?6 +6 v ?12 +12 v ?2.5 +2.5 v accuracy total unadjusted error (tue) b version 2 ?0.1 +0.1 % fsr ?0.05 0.02 +0.05 % fsr t a = 25c a version 2 ?0.3 +0.3 % fsr ?0.1 0.05 +0.1 % fsr t a = 25c relative accuracy (inl) ?0.02 0.005 +0.02 % fsr bipolar zero error (offset at midscale) ?10 +10 mv 10 v range ?8 0.5 +8 mv t a = 25c, 10 v range ?5 +5 mv 5 v range ?4 0.3 +4 mv t a = 25c, 5 v range bipolar zero error t emperature coefficient 3 1.5 ppm fsr/c all b ipolar ranges zero - scale error ?10 +10 mv 10 v range ?8 0.5 +8 mv t a = 25c, 10 v range ?5 +5 mv 5 v range ?4 0.3 +4 mv t a = 25c, 5 v range
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 5 of 36 parameter 1 min typ max unit test conditions/comments zero - scale error temperature coefficient 3 1 ppm fsr/c all b ipolar ranges zero - scale/offset error ?5 +5 mv 0 v to 10 v range ?4 0.5 +4 mv t a = 25c, 0 v to 10 v range ?3 +3 mv 0 v to 5 v range ?2.2 0.3 +2.2 mv t a = 25c, 0 v to 5 v range offset error temperature coefficient 3 2 ppm fsr/c all u nipolar range s gain error ?0.05 +0.05 % fsr all bipolar/unipolar ranges , ad5750 and ad5750 - 1 ?0.07 +0.07 % fsr ad5750 -2 ?0.04 0.015 +0.04 % fsr t a = 25c, ad5750 , ad5750 -1 , and ad5750 -2 gain error temperature coefficient 3 0.5 ppm fsr/c full - scale error ?0.05 +0.05 % fsr all bipolar/unipolar ranges, ad5750 and ad5750 - 1 ?0.04 0.015 +0.04 % fsr t a = 25c, ad5750 and ad5750 - 1 ?0.07 +0.07 % fsr ad5750 -2 full - scale error temperature coefficient 3 1.5 ppm fsr/c voltage output characteristics 3 headroom 1.3 v output unloaded short - circuit current 15 ma load 1 k? capacitive load stability t a = 25c r load = 1 nf r load = 2 k? 1 nf r load = 2 f external compensation capacitor required ; see the driving inductive loads section dc output impedance 0.12 ? leakage current ?110 +110 na output disabled; leakage to ground 0 v to 5 v range, ? to ? step 7 s specified with 2 k? || 220 pf, 0.05% 0 v to 5 v range, 40 mv input step 4.5 s specified with 2 k? || 220 pf, 0.05% slew rate 2 v/s specified with 2 k? || 220 pf output noise 2.5 v rms 0.1 hz to 10 hz bandwidth 45.5 v rms 100 khz bandwidth output noise spectral density 165 nv/hz measured at 10 khz; specified with 2 k? || 220 pf ac psrr ?65 db 200 mv, 50 hz/60 hz sine wave sup er- imposed on power supply voltage dc psrr 10 v/v outputs unloaded current output output current ranges 0 24 ma 0 20 ma 4 20 ma ?20 +20 ma ?24 +24 ma output current overranges 0 24.5 ma see the detailed description of features section 0 20.4 ma see the detailed description of features section 4 20.4 ma see the detailed description of features section
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 6 of 36 parameter 1 min typ max unit test conditions/comments accuracy, internal r set total unadjusted error (tue) b version 2 ?0.2 +0.2 % fsr ?0.08 0.03 +0.08 % fsr t a = 25c a version 2 ?0.5 +0.5 % fsr ?0.3 0.15 +0.3 % fsr t a = 25c relative accuracy (inl) ?0.02 0.01 +0.02 % fsr unipolar ranges ?0.03 0.015 +0.03 % fsr bipolar ranges offset error ?16 +16 a 4 ma to 20 ma, 0 ma to 20 ma, 0 ma to 24 ma ranges ?10 +5 +10 a t a = 25c ?50 +50 a 20 ma, 24 ma ranges ?26 +8 +26 a t a = 25c offset error temperature coefficient 3 3 ppm fsr/c all ranges bipolar zero error ?35 +35 a 20 ma, 24 ma ranges ?24 +15 +24 a t a = 25c bipolar zero temperature coefficient 3 0.5 ppm fsr/c gain error ?0.2 +0.2 % fsr 4 ma to 20 ma, 0 ma to 20 ma, 0 ma to 24 ma ranges ?0.25 +0.25 % fsr 20 ma, 24 ma ranges ?0.03 0.006 +0.03 % fsr t a = 25c gain temperature coefficient 3 8 ppm fsr/c all ranges full - scale error ?0.2 +0.2 % fsr all ranges ?0.125 0.02 +0.125 % fsr t a = 25c full - scale temperature coefficient 3 4 ppm fsr/c all ranges accuracy, external r set total unadjusted error (tue) b version 2 ?0.1 +0.1 % fsr ?0.08 0.03 +0.08 % fsr t a = 25 a version 2 ?0.3 +0.3 % fsr ?0.1 0.02 +0.1 % fsr t a = 25c relative accuracy (inl) ?0.02 0.01 +0.02 % fsr 4 ma to 20 ma, 0 ma to 20 ma, 0 ma to 24 ma ranges ?0.03 0.015 +0.03 % fsr 20 ma, 24 ma ranges offset error ?14 +14 a 4 ma to 20 ma, 0 ma to 20 ma, 0 ma to 24 ma ranges ?11 +5 +11 a t a = 25c ?20 +20 a 20 ma, 24 ma ranges +8 +15 a t a = 25c offset error temperature coefficient 3 2 ppm fsr/c all ranges bipolar zero error ?32 +32 a all ranges ?22 +12 +22 a t a = 25c bipolar zero temperature coefficient 3 0.5 ppm fsr/c gain error ?0.08 +0.08 % fsr all ranges ?0.07 0.02 +0.07 % fsr t a = 25c gain temperature coefficient 1 ppm fsr/c all ranges full - scale error ?0.1 +0.1 % fsr all ranges ?0.07 0.02 +0.07 % fsr t a = 25c full - scale temperature coefficient 3 2 ppm fsr/c all ranges
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 7 of 36 parameter 1 min typ max unit test conditions/comments current output characteristics 3 current loop compliance voltage 0 av dd ? 2.75 v resistive load see test conditions/comments column chosen such that compliance is not exceeded inductive load see test conditions/comments column needs appropriate capacitor at higher inductance values; see the driving inductive loads section settling time 4 ma to 20 ma, full - scale step 8.5 s 250 ? load 4 ma to 20 ma, 120 a step 1.2 s 250 ? load dc psrr 1 a/v output impedance 130 m? leakage current ?12 +12 na output disabled; leakage to ground vout/vsense? error 0.9994 1.0006 gain error in vout voltage due to changes in vsense?; specified as gain, for example, if vsense? moves by 1 v, vout moves by 0.9994 v digital input jedec compliant input high voltage, v ih 2 v input low voltage, v il 0.8 v input current ?1 +1 a per pin pin capacitance 5 pf per pin digital outputs 3 fault, ifault, temp, vfault output low voltage, v ol 0.4 v 10 k ? pull - up resistor to dv cc 0.6 v at 2.5 ma output high voltage, v oh 3.6 v 10 k ? pull - up resistor to dv cc sdo output low voltage, v ol 0.5 0.5 v sinking 200 a output high voltage, v oh dv cc ? 0.5 dv cc ? 0.5 v sourcing 200 a high impedance output capacitance 3 pf high impedance leakage current ?1 +1 a power requirements av dd 12 24 v 10% av ss ?12 ?24 v 10% dv cc input voltage 2.7 5.5 v ai dd 4.4 5.6 ma output unloaded, output disabled, r3, r2, r1, r0 = 0, 1, 0, 1 ; rset = 0 5.2 6.2 ma current output enabled 5.2 6.2 ma voltage output enabled ai ss 2.0 2.5 ma output unloaded, output disabled, r3, r2, r1, r0 = 0, 1, 0, 1 ; rset = 0, ad5750 and ad5750 - 1 2.0 3.5 ma ad5750 -2 2.5 3 ma current output enabled 2.5 3 ma voltage output enabled di cc 0.3 1 ma v ih = dv cc , v il = gnd power dissipation 108 mw av dd /av ss = 24 v, outputs unloaded 1 temperature range: ?40c to +105c; typical at +25c. 2 specification includes gain and offset errors over temperature and drift after 1000 hours, t a = 125c . 3 guaranteed by characterization, but not production tested.
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 8 of 36 timing characteristi cs av dd /av ss = 12 v ( 10%) to 24 v ( 10%) , dv cc = 2.7 v to 5.5 v, gnd = 0 v. vout: r load = 2 k?, c l = 200 pf, i out : r load = 300 ?. all specifications t min to t max , unless otherwise noted. table 3 . parameter 1 , 2 limit at t min , t max unit description t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 5 ns min sync falling edge to sclk falling edge setup time t 5 10 ns min 16 th sclk falling edge to sync rising edge (on 24 th sclk falling edge if using pec) t 6 5 ns min minimum sync high time (write mode) t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 , t 10 1.5 s max clear pulse low/high activation time t 11 5 ns min minimum sync high time (read mode) t 12 40 ns max sclk rising edge to sdo valid (sdo c l = 15 pf) t 13 10 ns min reset pulse low time 1 guaranteed by characterization, but not production tested. 2 all input signals are specified with t r = t f = 5 ns (10 % to 90% of dv cc ) and timed from a voltage level of 1.2 v.
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 9 of 36 timing diagrams figure 2 . write mode timing diagram figure 3. readback mode timing diagram d15 1 2 16 d0 t 1 t 2 t 5 t 8 t 7 t 3 sclk sync sdin clear vout t 10 t 9 t 13 reset t 4 t 6 07268-003 t 1 1 t 1 2 a 2 sd i n syn c sc l k a 0 r = 1 0 r3 r2 r1 r0 clrse l outen clear rset reset 0 0 a 1 x sd o x x x r 3 r 2 r 1 r 0 c l r s e l o u t e n r set pe c e rro r o ve r t e m p iou t f a u l t v o u t f a u l t x 07268-004
ad5750/ad5750-1/AD5750-2 data sheet rev. e | page 10 of 36 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 4. parameter rating av dd to gnd ?0.3 v to +30 v av ss to gnd +0.3 v to ?28 v av dd to av ss ?0.3 v to +58 v dv cc to gnd ?0.3 v to +7 v vsense+ to gnd av ss to av dd vsense? to gnd 5.0 v digital inputs to gnd ?0.3 v to dv cc + 0.3 v or +7 v (whichever is less) digital outputs to gnd ?0.3 v to dv cc + 0.3 v or +7 v (whichever is less) vref to gnd ?0.3 v to +7 v vin to gnd ?0.3 v to +7 v vout, iout to gnd av ss to av dd operating temperature range, industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 125c 32-lead lfcsp package ja thermal impedance 28c/w lead temperature jedec industry standard soldering j-std-020 esd (human body model) 3 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5750/ad5750-1/AD5750-2 rev. e | page 11 of 36 pin configuration and fu nction descriptions figure 4. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 sdo/vfault serial data output (sdo). in software mode, this pin is used to clock da ta from the input shift register in readback mode. data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. this pin is a cmos output. short-circuit fault alert (vfault). in hardware mode, th is pin acts as a short-circuit fault alert pin and is asserted low when a short-circuit error is detected. this pin is an open-drain output and must be connected to a pull-up resistor. 2 clrsel in hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. in software mode, this pin is implemented as a logic or with the internal clrsel bit. 3 clear active high input. asserting this pin sets the output current/voltage to zero -scale code or midscale code of the range selected (user selectable). clear is a logic or with the internal clear bit. in software mode, during power-up, the clear pin le vel determines the power-on condition of the voltage channel, which can be active 0 v or tristate. see th e asynchronous clear (clear) section for more details. 4 dv cc digital power supply. 5 gnd ground connection. 6 sync /rset positive edge sensitive latch (sync ). in software mode, a rising edge parallel loads the input shift register data into the ad5750/ ad5750-1/ AD5750-2 , also updating the output. resistor select (rset). in hardware mode, this pin selects whether the internal or the external current sense resistor is used. if rset = 0, the external sense resistor is chosen, and if rset = 1, the internal sense resistor is chosen. 7 sclk/outen serial clock input (sclk). in software mode, data is cloc ked into the input shift register on the falling edge of sclk. this pin operates at clock speeds up to 50 mhz. output enable (outen). in hardware mode , this pin acts as an output enable pin. 8 sdin/r0 serial data input (sdin). in software mode , data must be valid on the falling edge of sclk. range decode bit (r0). in hardware mode, this pin, in conjunction with r1, r2, and r3, selects the output current/voltage range setting on the part. 9 ad2/r1 device addressing bit (ad2). in software mode, this pin, in conjunction with ad1 and ad0, allows up to eight devices to be addressed on one bus. range decode bit (r1). in hardware mode, this pin, in conjunction with r0, r2, and r3, selects the output current/voltage range setting on the part. 10 ad1/r2 device addressing bit (ad1). in software mode, this pin, in conjunction with ad2 and ad0, allows up to eight devices to be addressed on one bus. range decode bit (r2). in hardware mode, this pin, in conjunction with r0, r1, and r3, selects the output current/voltage range setting on the part. pin 1 indicator top view (not to scale) ad5750/ ad5750-1/ AD5750-2 1 sdo/vfault 2 clrsel 3 clear 4 dv cc 5 gnd 6 sync/rset 7 sclk/outen 8 sdin/r0 24 vsense+ 23 vout 22 vsense? 21 av ss 20 comp1 19 comp2 18 iout 17 av dd 9 a d 2 / r 1 1 0 a d 1 / r 2 1 1 a d 0 / r 3 1 2 r e x t 2 1 3 r e x t 1 1 4 v r e f 1 5 v i n 1 6 g n d 3 2 n c / i f a u l t 3 1 f a u l t / t e m p 3 0 r e s e t 2 9 h w s e l e c t 2 8 n c 2 7 n c 2 6 n c 2 5 n c notes 1. nc = no conne c t. 2 . the exposed paddle is tied to avss. 07268-005
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 12 of 36 pin no. mnemonic description 11 ad0/r3 device addressing bit (ad0). in software mode, this pin, in conjunction with ad1 and ad2, allows up to eight devices to be addressed on one bus. range decode bit (r3). in hardware mode, this pin, in conjunction with r0, r1, and r2, selects the output current/voltage range setting on the part. 12, 13 rext2, rext1 a 15 k ? external current setting resistor can be connected between the rext1 and rext2 pins to improve the iout temperature drift performance. 14 vref buffered reference input. 15 vin buffered analog input (0 v to 4.096 v). 16 gnd ground connection. 17 av dd positive analog supply. 18 iout current output. 19, 20 comp2, comp1 optional compensation capacitor connection s for the voltage output buffer. the se pins are used to drive higher cap acitive loads on the output. the y also reduce overshoot on the output. c are should be taken when choosing the value of the capacitor connected between the comp1 and comp2 pins because it has a direct influence on the settling time of the output. see the driving large capacitive loads section for further details. 21 av ss negative analog supply. 22 vsense? sense connection for the negative voltage output load connection. this pin must stay within 3.0 v of ground for correct operation. 23 vout buffered analog output voltage. 24 vsense+ sense connection for the positive voltage output load connection. 25, 26, 27, 28 nc no connect. can be tied to gnd. 29 hw select this pin is used to configure the part to hardware or software mode. hw select = 0 selects software control, and hw select = 1 selects hardware control. 30 reset resets the part to its power - on state. 31 fault/temp fault alert (fault). in software mode, this pin acts as a general fault alert pin. it is asserted low when an open - circuit error , short - circuit error , overtemperature error, or pec interface error is detected. this pin is an open - drain output and must be connected to a pull - up resistor. overtemperature fault (temp). in hardware mode, this pin acts as an overtemperature fault pin. it is asserted low when an overtemperature error is detected. this pin is an ope n - drain output and must be connected to a pull - up resistor. 32 nc / i fau lt no connect (nc). in software mode, this pin is a no connect. instead, tie this pin to gnd. open - circuit fault alert (ifault). in hardware mode, this pin acts as an open - circuit fa ult alert pin. it is asserted low when an open - circuit error is detected. this pin is an open - drain output and must be connected to a pull - up resistor. epad the exposed paddle is tied to av ss .
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 13 of 36 typical performance characteristics voltage output figure 5 . integral nonlinearity error vs. v in figure 6 . integral nonlinearity error vs. temperature figure 7. total unadjusted error (tue) vs. v in figure 8 . total unadjusted error (tue) vs. temperature figure 9 . full - scale error vs. temperature figure 10 . bipolar zero error vs. temperature 0.0020 ?0.0030 ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 integral nonlinearity error (%fsr) v in (v) +5v +10v 5v 10v av dd = +24v av ss = ?24v 07268-105 0.005 ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 105 25 ?40 integral nonlinearity error (%fsr) temperature (c) av dd = +24v av ss = ?24v +5v linearity, no load +10v linearity, no load 5v linearity, no load 10v linearity, no load 07268-106 0.006 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0.004 0.002 0 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 tue (%fsr) v in (v) +5v +10v 5v 10v av dd = +24v av ss = ?24v 07268-107 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 105 25 ?40 tue (%fsr) temperature (c) +5v positive tue, no load +10v positive tue, no load 5v positive tue, no load 10v positive tue, no load +5v negative tue, no load +10v negative tue, no load 5v negative tue, no load 10v negative tue, no load 07268-108 0.03 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 105 25 ?40 full-scale error (%fsr) temperature (c) +5v range, full-scale error +10v range, full-scale error 5v range, full-scale error 10v range, full-scale error 07268-109 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 105 25 ?40 bipolar zero error (mv) temperature (c) 5v zero error 10v zero error av dd = +24v av ss = ?24v 07268-110
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 14 of 36 figure 11 . gain error vs. temperature figure 12 . zero - scale error (offset error) vs. temperature figure 13 . i ntegral nonlinearity error vs. supply voltage figure 14 . total unadjusted error (tue) vs. supply voltage s figure 15 . av dd headroom, 10 v range, output set to 10 v , load off figure 16 . source and sink capability of output amplifier 0.020 ?0.025 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 105 25 ?40 gain error (%fsr) temperature (c) av dd = +24v av ss = ?24v +5v gain, no load +10v gain, no load 5v gain, no load 10v gain, no load 07268-111 2.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.5 2.0 1.0 105 25 ?40 zero-scale error (mv) temperature (c) av dd = +24v av ss = ?24v output unloaded +5v range +10v range 5v range 10v range 07268-112 0.003 ?0.003 ?0.002 ?0.001 0 0.001 0.002 integral nonlinearity error (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +5v linearity, no load +10v linearity, no load 5v linearity, no load 10v linearity, no load 07268-113 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +5v positive tue, no load +10v positive tue, no load 5v positive tue, no load 10v positive tue, no load +5v negative tue, no load +10v negative tue, no load 5v negative tue, no load 10v negative tue, no load 07268-114 1.2 1.0 0.8 0.6 0.4 0.2 0 105 25 ?40 headroom (v) temperature (c) 10v v dd headroom, load off 07268-115 0.05 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 15 ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 1 3 5 7 9 11 13 output voltage delta (v) source/sink current (ma) +5v range 10v range 07268-116
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 15 of 36 figure 17 . full - scale positive step figure 18 . full - scale negative step figure 19 . v out vs. time on power - up, load = 2 k? || 200 pf figure 20 . v out enable glitch, load = 2 k? || 1 nf figure 21 . peak - to - peak noise (0.1 hz to 10 hz bandwidth) figure 22 . peak - to - peak noise (100 khz bandwidth) 12 10 8 6 4 2 0 27 22 17 12 7 2 ?3 ?8 voltage (v) time (s) 07268-117 12 10 8 6 4 2 0 27 22 17 12 7 2 ?3 ?8 voltage (v) time (s) 07268-118 40 35 30 25 20 15 10 5 0 ?5 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 v out (mv) time (ms) 07268-119 ch1 5.00v ch2 20.0mv b w m1.0s a ch1 3.00v 1 2 07268-120 5v/div 1s/div 07268-121 100v/div 1s/div 07268-122
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 16 of 36 figure 23 . v dd and v out vs. time on power - up 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.0 0.8 0.6 0.4 0.2 0 ?0.2 2.0 1.5 v dd v out 1.0 0.5 0 ?0.5 ?1.0 ?1.5 v dd (v) v out (v) time (ms) 07268-123
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 17 of 36 current output figure 24 . integral nonlinearity error vs. v in , external r set resistor figure 25 . integral nonlinearity error vs. v in , internal r set resistor figure 26 . integral nonlinearity error, current mode, external r set sense resistor figure 27 . integral nonlinearity error, current mode, internal r set sense resistor figure 28 . total unadjusted error (tue) vs. v in , external r set resistor figure 29 . total unadjusted error vs. v in , internal r set resistor 0.004 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0.002 0 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 integral nonlinearity error (%fsr) v in (v) av dd = +24v av ss = ?24v +4ma to +20ma 0ma to +20ma 0ma to +24ma 20ma 24ma 07268-124 0.004 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0.002 0 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 integral nonlinearity error (%fsr) v in (v) av dd = +24v av ss = ?24v +4ma to +20ma 0ma to +20ma 0ma to +24ma 20ma 24ma 07268-125 0.010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 integral nonlinearity error (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +4ma to +20ma external r set linearity 0ma to +20ma external r set linearity 0ma to +24ma external r set linearity 20ma external r set linearity 24ma external r set linearity 07268-126 0.010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 integral nonlinearity error (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +4ma to +20ma internal r set linearity 0ma to +20ma internal r set linearity 0ma to +24ma internal r set linearity 20ma internal r set linearity 24ma internal r set linearity 07268-127 0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 tue (%fsr) v in (v) av dd = +24v av ss = ?24v +4ma to +20ma 0ma to +20ma 0ma to +24ma 20ma 24ma 07268-128 0.015 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 tue (%fsr) v in (v) av dd = +24v av ss = ?24v +4ma to +20ma 0ma to +20ma 0ma to +24ma 20ma 24ma 07268-129
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 18 of 36 figure 30 . total unadjusted error (tue), current mode, external r set sense resistor figure 31 . total unadjusted error (tue), current mode, internal r set sense resistor figure 32 . i nl vs. temperature, internal r set sense resistor figure 33 . i nl vs. temperature, external r set sense resistor figure 34 . total unadjusted error (tue) vs. temperature, internal r set sense resistor figure 35 . total unadjusted error (tue) vs. temperature, external r set sense resistor 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +4ma to +20ma external r set positive tue 0ma to +20ma external r set positive tue 0ma to +24ma external r set positive tue 20ma external r set positive tue 24ma external r set positive tue +4ma to +20ma external r set negative tue 0ma to +20ma external r set negative tue 0ma to +24ma external r set negative tue 20ma external r set negative tue 24ma external r set negative tue 07268-130 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +4ma to +20ma internal r set positive tue 0ma to +20ma internal r set positive tue 0ma to +24ma internal r set positive tue 20ma internal r set positive tue 24ma internal r set positive tue +4ma to +20ma internal r set negative tue 0ma to +20ma internal r set negative tue 0ma to +24ma internal r set negative tue 20ma internal r set negative tue 24ma internal r set negative tue 07268-131 105 25 ?40 temperature (c) 0.010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 linearity (%fsr) +4ma to +20ma internal r set linearity 0ma to +20ma internal r set linearity 0ma to +24ma internal r set linearity 20ma internal r set linearity 24ma internal r set linearity av dd = +24v av ss = ?24v 07268-132 105 25 ?40 temperature (c) 0.010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 linearity (%fsr) +4ma to +20ma external r set linearity 0ma to +20ma external r set linearity 0ma to +24ma external r set linearity 20ma external r set linearity 24ma external r set linearity av dd = +24v av ss = ?24v 07268-133 105 25 ?40 temperature (c) 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) +4ma to +20ma internal r set positive tue 0ma to +20ma internal r set positive tue 0ma to +24ma internal r set positive tue 20ma internal r set positive tue 24ma internal r set positive tue +4ma to +20ma internal r set negative tue 0ma to +20ma internal r set negative tue 0ma to +24ma internal r set negative tue 20ma internal r set negative tue 24ma internal r set negative tue 07268-134 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) +4ma to +20ma external r set positive tue 0ma to +20ma external r set positive tue 0ma to +24ma external r set positive tue 20ma external r set positive tue 24ma external r set positive tue +4ma to +20ma external r set negative tue 0ma to +20ma external r set negative tue 0ma to +24ma external r set negative tue 20ma external r set negative tue 24ma external r set negative tue 105 25 ?40 temperature (c) 07268-135
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 19 of 36 figure 36 . zero - scale error vs. temperature, external r set sense resistor figure 37 . zero - scale error vs. temperature, internal r set sense resistor figure 38 . b ipolar zero - scale error vs. temperature, external r set sense resistor figure 39 . bipolar zero - scale error vs. temperature, internal r set sense resistor figure 40 . full - scale error vs. temperature, external r set sense resistor figure 41 . full - scale error vs. temperature, internal r set sense resistor 6 ?6 ?4 ?2 0 2 4 zero-scale error (a) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma external r set 0ma to +20ma external r set 0ma to +24ma external r set 20ma external r set 24ma external r set 07268-136 25 ?20 ?15 ?10 ?5 0 5 10 15 20 zero-scale error (a) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma internal r set 0ma to +20ma internal r set 0ma to +24ma internal r set 20ma internal r set 24ma internal r set 07268-137 3 ?5 ?4 ?3 ?2 ?1 0 1 2 bipolar zero-scale error (a) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v 20ma, external r set 24ma, external r set 07268-138 2 ?6 ?5 ?4 ?3 ?2 ?1 0 1 bipolar zero-scale error (a) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v 20ma, internal r set 24ma, internal r set 07268-139 0.04 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 full-scale error (%fsr) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma external r set 0ma to +20ma external r set 0ma to +24ma external r set 20ma external r set 24ma external r set 07268-140 0.04 ?0.06 ?0.04 ?0.05 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 full-scale error (%fsr) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma internal r set 0ma to +20ma internal r set 0ma to +24ma internal r set 20ma internal r set 24ma internal r set 07268-141
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 20 of 36 figure 42 . gain error vs. temperature, external r set sense resistor figure 43 . gain error vs. temperature , internal r set sense resistor figure 44 . output compliance vs. temperature tested when i out = 10.8 ma, 24 ma range selected figure 45 . v dd and output current (i out ) vs. time - o n power - up figure 46 . output current (i out ) vs. time - o n output enable figure 47 . 4 ma to 20 ma output current step 0.020 0.015 ?0.015 ?0.010 ?0.005 0 0.005 0.010 gain error (%fsr) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma external r set 0ma to +20ma external r set 0ma to +24ma external r set 20ma external r set 24ma external r set 07268-142 0.08 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.04 0.02 0.06 gain error (%fsr) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma internal r set 0ma to +20ma internal r set 0ma to +24ma internal r set 20ma internal r set 24ma internal r set 07268-143 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 compliance (v) 105 25 ?40 temperature (c) av dd compliance av ss compliance 07268-144 12 10 8 6 4 2 0 ?2 0.000010 ?0.000010 ?0.000008 ?0.000006 ?0.000004 ?0.000002 0 0.000002 0.000004 0.000006 0.000008 10 v dd i out ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 v dd (v) i out (a) time (ms) 07268-145 0 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 8 ?2 ?1 0 1 2 3 4 5 6 7 i out (v) time (s) 07268-146 0.025 0.020 0.015 0.010 0.005 0 68 61 54 48 41 34 28 21 14 8 1 ?12 ?6 current (a) time (s) 07268-147
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 21 of 36 figure 48 . di cc vs. logic input voltage figure 49 . ai dd /ai ss vs. av dd /av ss , v out = 0 v figure 50 . ai dd /ai ss vs. av dd /av ss , i out = 0 ma 3000 2500 2000 1500 1000 500 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 di cc (a) logic level (v) dv cc = 5v dv cc = 3v 07268-148 6 5 4 3 2 1 0 ?1 ?2 ?3 ai dd /ai ss (ma) av dd /av ss (v) 10.8 15.0 24.0 26.4 ai dd ai ss 07268-149 6 5 4 3 2 1 0 ?1 ?2 ?3 ai dd /ai ss (ma) av dd /av ss (v) 10.8 15.0 24.0 26.4 ai dd ai ss 07268-150
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 22 of 36 terminology total unadjusted error (tue) tue is a measure of the output error taking all the various errors into account: inl error, offset error, gain error, and output drift over supplies, temperature, and time. tue is expressed as a percentage of full - scale range (% fsr) . relative accuracy or integral nonlinearity (inl) inl is a measure of the maximum deviation, in % fsr, from a straight line passing through the endpoints of the output driver transfer function. a typical inl vs. input voltage plot can be seen in figur e 5 . bipolar zero error bipolar zero error is the deviation of the actual vs . ideal half - scale output of 0 v/0 ma with a bipolar range selected. a plot of bipolar zero error vs. temperatu re can be seen in figure 10. bipolar zero t emperature coefficient (tc) bipolar zero tc is a measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. full - scale erro r full - scale error is the deviation of the actual full - scale analog output from the ideal full - scale output. full - scale error is expressed as a percentage of full - scale range (% fsr). full - scale temperature coefficient (tc) full - scale tc is a measure of the change in the full - scale error with a change in temperature. it is expressed in ppm fsr/c. gain error gain error is a measure of the span error of the output. it is the deviation in slope of the output transfer characteristic from the ideal express ed in % fsr. a plot of gain error vs. temperature can be seen in figure 11. gain error temperature coefficient (tc) gain error tc is a measure of the change in gain error with changes in temperature. gain error tc is expressed in ppm fsr/c. zero - scale error zero - scale error is the deviation of the actual zero - scale analog output from the ideal zero - scale output. zero - scale error is expressed in millivolts (mv). zero - scale tc zero - scale tc is a measure of the change in zero - scale error with a change in temperature. zero - scale error tc is expressed in ppm fsr/c. offset error offset error is a measurement of the difference between the actual vout and the ideal vout , expressed in millivolts ( mv ) in the linear region of the transfer function. it can be negative or positive. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified l evel for a half - scale input change. slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed is usually limited by the slew rate of the amplifier used at its output. slew rate is measured f rom 10% to 90% of the output signal and is expressed in v/ s. current loop voltage compliance current loop voltage compliance is the maximum voltage at the iout pin for which the output current is equal to the programmed value. power - on glitch energy p ower - on glitch energy is the impulse injected into the analog output when the ad5750 / ad5750 - 1 / ad5750 - 2 are powered on . it is specified as the area of the glitch in nv - sec. power supply rejection ratio (psrr) psrr indicates how the output is affected by changes in the power supply voltage.
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 23 of 36 theory of operation the ad5750 / ad5750 - 1 / ad5750 - 2 are single - channel, precision voltage/current output driver s with hardware - or software - programmable output ranges. the software ranges are configured via an spi - /microwire - compatible serial interface. the analog input to the ad5750 / ad5750 - 1 / ad5750 - 2 is provided from a low voltage, single - supply dac and is internally conditioned to provide the desired output current/voltage range. analog input ranges available are 0 v to 2.5 v ( ad5750 - 1 / ad5750 - 2 ) or 0 v to 4.096 v ( ad5750 ). the output current range is programmable across five current ranges: + 4 ma to + 20 ma, 0 ma to + 20 ma , 0 ma to + 24 ma, 20 ma , and 24 ma . the voltage output is provided from a separate pin that can be configured to provide 0 v to +5 v, 0 v to +10 v, 5 v, or 10 v output ranges. an overrange of 20% is a vailable on the voltage ranges. an overrange of 2 % is available on the 4 ma to 20 ma, 0 ma to 20 ma , and 0 ma to 24 ma current ranges. the current and voltage outputs are available on separate pins. only one output can be enabled at one time. the output range is selected by programming the r3 to r0 bits in the control register (see table 7 and table 8 ). figure 51 and figure 52 show a typical configuration of the ad5750 / ad5750 - 1 / ad5750 - 2 in software mode and in hardware mode, respectively, in an output module system. the hw select pin selects whether the part is configured in softw are or hardware mode. the analog input to the ad5750 / ad5750 - 1 / ad5750 - 2 is provided from a low voltage, single - supply dac , such as the ad506 x or ad566 x , which provides an output range of 0 v to 4.096 v. the supply and reference for the dac, as well as the reference for the ad5750 / a d5750 - 1 / ad5750 - 2 , can be supplied from a reference such as the adr392 . the ad5750 / ad5750 - 1 / ad5750 - 2 can operate from supplies up to 26.4 v. software mode in current mode, software - selectable output ranges include 20 ma, 24 ma, 0 ma to +20 ma , +4 ma to +20 ma, and 0 ma to + 24 ma. in voltage mode, software - selectable output ranges include 0 v to + 5 v, 0 v to + 10 v, 5 v, and 10 v . figure 51 . typical system configuration in software mode (pull - up resistors not shown for open - drain outputs) 07268-045 vsense+ vsense? vin sclk vdd refin sdi/din sdo sync1 sync sdo sdin sclk ad506x ad566x mcu vout 0v t o +5 v , 0v t o +10 v , 5 v , 10v iout 0m a t o +20ma, 0m a t o +24ma, +4m a t o +20m a 20ma, 24m a vout range scale iout range scale vout short f au l t iout open f au l t overtem p f au l t sta tus register seria l inter f ace vref hw select f au l t adp1720 adr392 vdd agnd vss a v dd gnd a v ss ad5750/ ad5750-1/ AD5750-2
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 24 of 36 figure 52 . typical system configuration in hardware mode using internal dac reference (pull - up resistors not shown for open - drain outputs) table 6 . sugg ested parts for use with ad5750 , ad5750 - 1 , and ad5750 - 2 dac reference power accuracy description ad5660 internal adp1720 1 12- bit inl midend system, single channel, internal reference ad5664r internal not applicable not applicable midend system, quad channel, internal reference ad5668 internal not applicable not applicable midend system, octal channel, internal reference ad5060 adr434 adp1720 1 16- bit inl high end system, single channel, external reference ad5064 adr434 not applicable not applicable high end system, quad channel, external reference ad5662 adr392 2 adr392 2 12- bit inl midend system, single channel, external reference ad5664 adr392 2 not appli cable not applicable midend system, quad channel, external reference 1 the input range of the adp1720 is up to 28 v . 2 the input range of the adr392 is up to 15 v . 07268-046 vsense+ vsense? r3 r2 r1 r0 output range select pins vin sclk vdd refin sdi/din sdo sync1 ad506x ad566x mcu vout 0v t o +5 v , 0v t o +10 v , 5 v , 10v iout 0m a t o +20ma, 0m a t o +24ma, +4m a t o +20m a 20ma, 24m a vout range scale iout range scale vref tem p vf au l t if au l t adp1720 adr392 vdd agnd vss outen hw select dv cc a v dd gnd a v ss ad5750/ ad5750-1/ AD5750-2
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 25 of 36 current output archi tecture the voltage input from the analog input vin pin (0 v to 4.096 v for ad5750 and 0 v to 2.5 v for the ad5750 - 1 / ad5750 - 2 ) is either converted to a current (see figure 53 ), which is then mirrored to the supply rail so that the application simply sees a current source output with respect to an internal reference voltage, or it is buffered and scaled to output a software - selectable unipolar or bipolar vol tage range (see figure 54 ). the reference is used to provide internal offsets for range and gain scaling. the selectable output range is programmable through the digital interface. figure 53 . current output configuration figure 54 . voltage output driving inductive lo ads when driving inductive or poorly defined loads, connect a 0.01 f capacitor between iout and gnd. this ensures stability with loads beyond 50 mh. there is no maximum capacitance limit. the capacitive component of the load may cause slower settling. voltage output amplifier the voltage output amplifier is capable of generating both unipolar and bipolar output voltages. it is capable of driving a load of 1 k? in parallel with 1.2 f (with an external compensation capacitor on the comp1 and comp2 pins). the source and sink capabilities of the output amplifier can be seen in figure 16 . the slew rate is 2 v/s. internal to the device, there is a 2.5 m? resistor connected between the vout and vsense+ pins and , similarly , between the vsense? pin and the internal device ground. if a fault condition occur s , these resistors act to protect the ad5750 / ad5750 - 1 / ad5750 - 2 by ensuring that the amplifier loop is closed so that the part does not enter into an open - loop condition. the vsense? pin can work in a common - mode range of 3 v with respect to the remote load ground point. the current and voltage are output on separate pins and cannot be output simultaneously. this allows the user to tie both the current and voltage output pins together and confi gure the end system as a single channel output. driving large capacitive loads the voltage out put amplifier is capable of driving capacitive loads of up to 1 f with the addition of a nonpolarized compensation capacitor between the comp1 and comp2 pins. without the compensation capacitor, up to 20 nf capacitive loads can be driven. care should be t aken to choose an appropriate value for the c comp capacitor. this capacitor, while allowing the ad5750 / ad5750 - 1 / ad5750 - 2 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and , therefore , affects the bandwidth of the system. considered values of this capacitor should be in the range 100 pf to 4 nf , depending on the trade - o ff required between settling time, overshoot, and bandwidth. power - on state of ad5750 / ad5750 - 1 / ad5750 - 2 on power - up, the ad5750 / ad5750 - 1 / ad5750 - 2 sense whether hardware or software mode is loaded and set the power - up conditions accor dingly. in software spi mode, the power - up state of the output is dependent on the state of the clear pin. if the clear pin is pulled high, the part powers up, driving an active 0 v on the output. if the clear pin is pulled low, the part powers up with the voltage output channel in tristate mode. in both cases, the current output channel powers up in the tristate condition (0 ma). this allows the voltage and current outputs to be connected together , if desired. to put the part into normal operation, the user must set the outen bit in the control register to enable the output and, in the same write, set the output range configuration using the r3 to r0 range bits. if the clear pin is still high (active) during thi s write, the part automatically clears to its normal clear state as defined by the programmed range and by the clrsel pin or the clrsel bit (see the asynchronous clear (clear) section for more details). to operate the part in normal mode, take t he clear pin low. the clear pin is typically driven directly from a microcontroller. in cases where the power supply for the ad5 750 / ad5750 - 1 / ad5750 - 2 supply may be independent of the microcontroller power supply, connect a weak pull - up resistor to dv cc or a pull - down resistor to ground to ensure that the correct power - up condition is achieved independent of the microcontroller. a 10 k? pull - up/pull - down resistor on the clear pin should be sufficient for most applications. if hardware mode is selected, the part powers up to the conditions defined by the r3 to r0 range bits and the status of the outen or clear pin. it is recommended to keep the output disabled when powering up the part in hardware mode. iout range scaling rext1 iout r set vx v ss v dd r1 r4 r2 r3 rext2 iout open fault vin vref range decode from interface 07268-047 vout range scaling vsense+ vout vsense? vout short fault range decode from interface vin (0v to 4.096v) vref 07268-048
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 26 of 36 default registers at power - on the ad5750 / ad5750 - 1 / ad5750 - 2 power - on - reset circuit ensures that all registers are loaded with zero code. in software spi mode, the part powers up with a ll outputs disabled (outen bit = 0). the user must set the outen bit in the control register to enable the output and, in the same write, to set the output range configuration using the r3 to r0 bits. if hardware mode is selected, the part powers up to th e conditions defined by the r3 to r0 bits and the status of the outen pin. it is recommended to keep the output disabled when powering up the part in hardware mode. reset function in software mode, the part can be reset using the reset p in (active low) or the reset bit (reset = 1). a reset disables both the current and voltage outputs to their power - on condition. the user must write to the outen bit to enable the output and, in the same write, to set the output range configuration. the reset pin is a level - sensitive input; the part stays in reset mode as long as the reset pin is low. the reset bit clears to 0 following a reset command to the control register. in hardware mode, there is no reset. if usin g the part in hardware mode, tie the reset pin high. outen in software mode, the output can be enabled or disabled using the outen bit in the control register. when the output is disabled, both the current and voltage channels go into tristate. the user must set the outen bit to enable the output and simultaneousl y set the output range configuration. in hardware mode, the output can be enabled or disabled using the outen pin. when the output is disabled, both the current and voltage channels go into tristate. the user must write to the outen pin to enable the outpu t. it is recommended that the output be disabled when changing the ranges. software control software control is enabled by connecting the hw select pin to ground. in software mode, the ad5750 / ad5750 - 1 / ad5750 - 2 are controlled over a versatile 3 - wire serial interface that operates at clock rates up to 50 mhz. it is compatible with spi, qspi?, microwire, and dsp standards. input shift register the input shift register is 16 bits wide. data is loaded into the device msb first as a 16 - bit word under the control of the serial clock input, sclk. data is clocked in on the falling edge of sclk. the input shift register consists o f 16 control bits , as shown in table 7 . the timing diagram for this write operation is shown in figure 2 . the first three bits of the input shift register are used to set the hardware address of the ad5750 / ad5750 - 1 / ad5750 - 2 device on the printed circuit board (pcb). up to eight devices can be addressed per board. bit d11, bit d1, and bit d0 must always be set to 0 during any write sequence. ta ble 7 . input shift register contents for a write operation control register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a2 a1 a0 r/ w 0 r3 r2 r1 r0 clrsel outen clear rset reset 0 0 table 8 . input shift register descriptions bit description a2, a1, a0 used in association with the ad2, ad1, and ad0 external pins to determine which part is being addressed by the system controller. a2 a1 a0 function 0 0 0 addresses part with pin ad2 = 0, pin ad1 = 0, pin ad0 = 0 . 0 0 1 addresses part with pin ad2 = 0, pin ad1 = 0, pin ad0 = 1 . 0 1 0 addresses part with pin ad2 = 0, pin ad1 = 1, pin ad0 = 0 . 0 1 1 addresses part with pin ad2 = 0, pin ad1 = 1, pin ad0 = 1 . 1 0 0 addresses part with pin ad2 = 1, pin ad1 = 0, pin ad0 = 0 . 1 0 1 addresses part with pin ad2 = 1, pin ad1 = 0, pin ad0 = 1 . 1 1 0 addresses part with pin ad2 = 1, pin ad1 = 1, pin ad0 = 0 . 1 1 1 addresses part with pin ad2 = 1, pin ad1 = 1, pin ad0 = 1 . r/ w indicates a read from or a write to the addressed register.
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 27 of 36 bit description r3, r2, r1, r0 selects the output configuration in conjunction with rset. rset r3 r2 r1 r0 output configuration 0 0 0 0 0 4 ma to 20 ma (external 15 k? current sense resistor) . 0 0 0 0 1 0 ma to 20 ma (external 15 k? current sense resistor) . 0 0 0 1 0 0 ma to 24 ma (external 15 k? current sense resistor) . 0 0 0 1 1 20 ma (external 15 k? current sense resistor) . 0 0 1 0 0 24 ma (external 15 k? current sense resistor) . 0 0 1 0 1 0 v to 5 v . 0 0 1 1 0 0 v to 10 v . 0 0 1 1 1 5 v . 0 1 0 0 0 10 v . 0 1 0 0 1 0 v to 6.0 v (20% overrange) . 0 1 0 1 0 0 v to 12.0 v (20% overrange) . 0 1 0 1 1 6.0 v (20% overrange) . 0 1 1 0 0 12.0 v (20% overrange) . 0 1 1 0 1 2.5 v . 0 1 1 1 0 not applicable ; if selected, output drives between 0 v and ?1 v . 0 1 1 1 1 not applicable ; if selected, output drives between 0 v and ?1 v . 1 0 0 0 0 4 ma to 20 ma (internal current sense resistor) . 1 0 0 0 1 0 ma to 20 ma (internal current sense resistor) . 1 0 0 1 0 0 ma to 24 ma (internal current sense resistor) . 1 0 0 1 1 20 ma (internal current sense resistor) . 1 0 1 0 0 24 ma (internal current sense resistor) . 1 0 1 0 1 0 v to 5 v . 1 0 1 1 0 0 v to 10 v . 1 0 1 1 1 5 v . 1 1 0 0 0 10 v . 1 1 0 0 1 0 v to 6.0 v (20% overrange). 1 1 0 1 0 0 v to 12.0 v (20% overrange) . 1 1 0 1 1 6.0 v (20% overrange) . 1 1 1 0 0 12.0 v (20% overrange) . 1 1 1 0 1 3.92 ma to 20.4 ma (internal current sense resistor) . 1 1 1 1 0 0 ma to 20.4 ma (internal current sense resistor) . 1 1 1 1 1 0 ma to 24.5 ma (internal current sense resistor) . clrsel sets clear mode to zero scale or midscale. see the asynchronous clear (clear) section. clrsel function 0 clear to 0 v . 1 clear to midscale in unipolar mode; clear to zero scale in bipolar mode . outen output enable bit. this bit must be set to 1 to enable the outputs. clear software clear bit, active high. rset select internal/external current sense resistor. rset function 1 select internal current sense resistor; used with r3 to r0 bits to select range . 0 select external current sense resistor; used with r3 to r0 bits to select range . reset resets the part to its power - on state.
ad5750/ad5750 - 1/ad5750 - 2 data sheet rev. e | page 28 of 36 status bit read operation a read of the status bits can be initiated as part of a normal write operation. the read is activated by selecting the correct device address (a2, a1, a0) and then setting the r/ w bit to 1. by default, the sdo pin is disabled. after having addressed the ad5750 / ad5750 - 1 / ad5750 - 2 and setting r/ w to 1 the sdo pin is enabled and data is clocked out on the 5 th rising edge of sclk. after all the data has been clocked out on sdo, a rising edge on sync disables (tri states) the sdo pin again. status register data (see table 9 ) and control register data are both available during the same read cycle. data contained in bit d10 to bit d0 of the write operation are still valid and can be used to chan ge the operating mo d e of the ad5750 / ad5750 - 1 / ad5750 - 2 if required. the status bits comprise three read - only bits. they are used to notify the user of specific fault conditions that occur, such as an open circuit or short circuit on the output, an overtemperature error, or an interface error. if any of these fault conditions occur, a hardware fault is also asserted low, which can be used as a hardware interrupt to the controller. see the detailed description of features section for a full explanation of fault c onditions. hardware control hardware control is enabled by connecting the hw select pin to dv cc . in this mode, the r3, r2, r1, and r0 p ins , in conjunction with the rse t pin , are used to configure the output range per table 8 . in hardware mode, there is no status register. the fault conditions (open circuit, short circuit, and overtemperature) are available on the ifault, v fault, and t e mp pins . if any one of these fault conditions are set, a low is asserted on the specific fault pin . ifault, v fault, and t e mp are op e n - drain outputs and , therefore , can be connected together to allow the user to generate one interrupt to the system controller to communicate a fault. if hardwired in this way, it is not possible to isolate which fault occurred in the system. transfer function the ad5750 / ad5750 - 1 / ad5750 - 2 consist of an internal signal conditioning block that maps the analog input voltage to a programmed output range. the available analog input ranges are 0 v to 4.096 v ( ad5750 ) and 0 v to 2.5 v ( ad5750 - 1 / ad5750 - 2 ). for all ranges, both current and voltage, the ad5750 , ad5750 - 1 , and ad5750 - 2 implement a straight linear mapping function , where 0 v maps to the lower end of the selected range and 4.096 v (or 2.5 v for ad5750 - 1 / ad5750 - 2 ) maps to the upper end of the selected range. table 9 . input shift register contents for a read operation status register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a2 a1 a0 1 0 r3 r2 r1 r0 clrsel outen rset pec e rror over temp iout f ault vout f ault table 10 . status bit options bit description pec error this bit is set if there is an interface error detected by crc - 8 error checking. see the detailed description of features section. over temp this bit is set if the ad5750 / ad5750 - 1 / ad5750 - 2 core temperature exceeds approximately 150c. iout fault this bit is set if there is an open circuit on the iout pin. vout fault this bit is set if there is a short circuit on the vout pin.
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 29 of 36 detailed description of featu res output fault alert software mode in software mode, the ad5750 / ad5750 - 1 / ad5750 - 2 are equipped with one fault pin; this is an open - drain output allowing several ad5750 / ad5750 - 1 / ad5750 - 2 devices to be connected together to one pull - up resistor for global fault detection. in software mode, the fault pin is forced active low by any one o f the following fault scenarios: ? the voltage at iout attempts to rise above the compliance range due to an open - loop circuit or insufficient power supply voltage. the internal circuitry that develops the fault output avoids using a comparator with window l imits because this requires an actual output error before the fault output becomes active. instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 v of remaining drive capability. thus, the fault outpu t activates slightly before the compliance limit is reached. because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open - loop gain, and an output error does not occur before the fault outpu t becomes active. ? a short is detected on the voltage output pin (vout). the short - circuit current is limited to 15 ma. ? an interface error is detected due to pec failure. see the packet error checking section. ? t he core temperature of the ad5750 / ad5750 - 1 / ad5750 - 2 exceeds approximately 150c. output fault alert hardware mode in hardware mode, the ad5750 / ad5750 - 1 / ad5750 - 2 are equipped with three fault pins : vfault, ifault, and temp. these are open - drain outputs allowing several ad5750 / ad5 750 - 1 / ad5750 - 2 devices to be connected together to one pull - up resistor for global fault detection. in hardware control mode, these fault pins are forced active by any one of the following fault scenarios: ? an open circuit is detect ed . the voltage at iout attempts to rise above the compliance range, due to an open - loop circuit or insufficient power supply voltage. the internal circuitry that develops the fault output avoids using a comparator with window limi ts because this requires an actual output error before the fault output becomes active. instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 v of remaining drive capability. thus, the fault output a ctivates slightly before the compliance limit is reached. because the compari son is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open - loop gain, and an output error does not occur before the fault output b ecomes active. if this fault is detected, the ifault pin is forced low. ? a short is detected on the voltage output pin (vout). the short - circuit current is limited to 15 ma. if this fault is detected, the vfault pin is forced low. ? t he core temperature of the ad5750 / ad5750 - 1 / ad5750 - 2 exceeds approximately 150c. if this fault is detected, the temp pin is forced low. volt age output short - circuit protection under normal oper ation, the voltage output sinks and sources up to 12 ma and maintains specified operation. the maximum current that the voltage output delivers is 15 ma; this is the short - circuit current. asynchronous c lear (clear) clear is an active high clear that allows the voltage output to be cleared to either zero - scale code or midscale code and is user - selectable via the clrsel pin or the clrsel bit of the input shift register, as described in table 8 . (the clear select feature is a logical or function of the clrsel pin and the clrsel bit). the current loop output clears to the bottom of its programmed range. when the clear signal is returned low, the output returns to its programmed value or to a new programmed value. a clear operation can also be performed via the clear command in the control register (see table 11) . table 11 . clrsel options clrsel output clear value unipolar output voltage range unipolar current output range bipolar output range bipolar current output range 0 0 v zero scale; for example, 4 ma on the 4 ma to 20 ma range , 0 ma on the 0 ma to 20 ma range negative full scale zero scale; for example, ?24 ma on the 24 ma range 1 midscale midscale; for example, 12 ma on the 4 ma to 20 ma range , 10 ma on the 0 ma to 20 ma range 0 v midscale; for example, 0 ma on the 24 ma range
ad5750/ad5750-1/AD5750-2 data sheet rev. e | page 30 of 36 external current setting resistor referring to figure 1, r set is an internal sense resistor and is part of the voltage-to-current conversion circuitry. the nominal value of the internal current sense resistor is 15 k. to allow for overrange capability in current mode, the user can also select the internal current sense resistor to be 14.7 k, giving a nominal 2% overrange capability. this feature is available in the 0 ma to +20 ma, +4 ma to +20 ma, and 20 ma current ranges. the stability of the output current value over temperature is dependent on the stability of the value of r set . as a method of improving the stability of the output current over temperature, an external low drift resistor can be connected to the rext1 and rext2 pins of the ad5750/ ad5750-1 / AD5750-2 , which can be used instead of the internal resistor. the external resistor is selected via the input shift register. if the external resistor option is not used, leave the rext1 and rext2 pins floating. programmable overrange modes the ad5750/ ad5750-1 / AD5750-2 contain an overrange mode for most of the available ranges. the overranges are selected by configuring the r3, r2, r1, and r0 bits (or pins) accordingly. in voltage mode, the overranges are typically 20%, providing programmable output ranges of 0 v to +6 v, 0 v to +12 v, 6 v, and 12 v. the analog input remains the same. in current mode, the overranges are typically 2%. in current mode, the overrange capability is available on only three ranges, 0 ma to 20 ma, 0 ma to 24 ma, and 4 ma to 20 ma. for these ranges, the analog input also remains the same (0 v to 4.096 v for the ad5750 , and 0 v to 2.5 v for the ad5750-1 / AD5750-2 ). packet error checking to verify that data has been received correctly in noisy environ- ments, the ad5750 / ad5750-1 / AD5750-2 offer the option of error checking based on an 8-bit cyclic redundancy check (crc-8). the device controlling the ad5750/ ad5750-1 / AD5750-2 should generate an 8-bit frame check sequence using the following polynomial: c ( x ) = x 8 + x 2 + x 1 + 1 this is added to the end of the data-word, and 24 data bits are sent to the ad5750/ ad5750-1 / AD5750-2 before taking sync high. if the ad5750 / ad5750-1 / AD5750-2 receive a 24-bit data frame, the parts perform the error check when sync goes high. if the check is valid, the data is written to the selected register. if the error check fails, the fault pin goes low, and bit d3 of the status register is set. after reading this register, this error flag is cleared automatically, and the fault pin goes high again. figure 55. pec error checking timing sclk sdin sync update on sync high d15 (msb) d0 (lsb) 16-bit data 16-bit data transer?no error checking sclk sdin sync fault update after sync high only if error check passed fault goes low if error check fails d23 (msb) d8 (lsb) d7 d0 16-bit data 8-bit fcs 16-bit data transer with error checking 07268-049
data sheet ad5750/ad5750-1/AD5750-2 rev. e | page 31 of 36 applications information transient voltage protection the ad5750 / ad5750-1/ AD5750-2 contain esd protection diodes that prevent damage from normal handling. the industrial control environment can, however, subject i/o circuits to much higher transients. to protect the ad5750/ ad5750-1 / AD5750-2 from excessively high voltage transients, external power diodes and a surge current limiting resistor may be required, as shown in figure 56. the constraint on the resistor value is that during normal operation the output level at iout must remain within its voltage compliance limit of av dd ? 2.75 v and the two protection diodes and resistor must have appropriate power ratings. further protection can be added with transient voltage suppressors, if needed. figure 56. output transient voltage protection thermal considerations it is important to understand the effects of power dissipation on the package and how it affects junction temperature. the internal junction temperature should not exceed 125c. the ad5750/ ad5750-1 / AD5750-2 are packaged in a 32-lead, 5 mm 5 mm lfcsp package. the thermal impedance, ja , is 28c/w. it is important that the devices are not being operated under conditions that cause the junction temperature to exceed its junction temperature. worst-case conditions occur when the ad5750/ ad5750-1 / AD5750-2 are operated from the maximum av dd (26.4 v) and are driving the maximum current (24 ma) directly to ground. the quiescent current of the ad5750/ ad5750-1 / AD5750-2 should also be taken into account, nominally ~4 ma. the following calculations estimate maximum power dissipation under these worst-case conditions and determine the maximum ambient temperature: power dissipation = 26.4 v 28 ma = 0.7392 w temperature increase = 28c 0.7392 w = 20.7c maximum ambient temperature = 125c ? 20.7c = 104.3c these figures assume that proper layout and grounding techniques are followed to minimize power dissipation, as outlined in the layout guidelines section. layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the pcb on which the ad5750/ ad5750-1 / AD5750-2 are mounted should be designed so that the ad5750 / ad5750-1 / AD5750-2 lie on the analog plane. the ad5750/ ad5750-1 / AD5750-2 should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the ad5750 / ad5750-1/ AD5750-2 have an exposed paddle beneath the device. connect this paddle to the av ss supply of the part. for optimum performance, use special considerations to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, solder the exposed paddle on the bottom of the package to the corresponding thermal land paddle on the pcb. design thermal vias into the pcb land paddle area to further improve heat dissipation. the av ss plane on the device can be increased (as shown in figure 57) to provide a natural heat sinking effect. figure 57. paddle connection to board iout av dd a v dd av ss r p r load 07268-050 ad5750/ ad5750-1/ AD5750-2 a d5750/ ad5750-1/ AD5750-2 av ss plane board 07268-051
ad5750/ad5750-1/AD5750-2 data sheet rev. e | page 32 of 36 galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. the icoupler? family of products from analog devices, inc., provides voltage isolation in excess of 5.0 kv. the serial loading structure of the ad5750/ ad5750-1 / AD5750-2 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 58 shows a 4-channel isolated interface using an adum1400 . for further information, visit www.analog.com/icouplers . figure 58. isolated interface microprocessor interfacing microprocessor interfacing to the ad5750/ ad5750-1 / AD5750-2 is via a serial bus that uses a protocol that is compatible with microcontrollers and dsp processors. the communication channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a sync signal. the ad5750 / ad5750-1 / AD5750-2 require a 16-bit data-word with data valid on the falling edge of sclk. decode encode v ia v oa to sclk v ib v ob to sdin v ic v oc to sync v id v od to clear serial clock out serial data out sync out control out controller adum1400 1 1 additional pins omitted for clarity. decode encode decode encode decode encode 07268-052
data sheet ad5750/ad5750-1/AD5750-2 rev. e | page 33 of 36 outline dimensions figure 59. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model 1 tue accuracy (%) analog input range (v) external reference (v) temperature range package description package option ad5750acpz 0.3 0 to 4.096 4.096 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750acpz-reel 0.3 0 to 4.096 4.096 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750acpz-reel7 0.3 0 to 4.096 4.096 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750bcpz 0.1 0 to 4.096 4.096 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750bcpz-reel 0.1 0 to 4.096 4.096 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750bcpz-reel7 0.1 0 to 4.096 4.096 ?40c to +105c 32-lead lfcsp_vq cp-32-2 eval-ad5750ebz evaluation board ad5750-1acpz 0.3 0 to 2.5 1.25 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750-1acpz-reel 0.3 0 to 2.5 1.25 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750-1acpz-reel7 0.3 0 to 2.5 1.25 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750-1bcpz 0.1 0 to 2.5 1.25 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750-1bcpz-reel 0.1 0 to 2.5 1.25 ?40c to +105c 32-lead lfcsp_vq cp-32-2 ad5750-1bcpz-reel7 0.1 0 to 2.5 1.25 ?40c to +105c 32-lead lfcsp_vq cp-32-2 AD5750-2bcpz 0.1 0 to 2.5 2.5 ?40c to +105c 32-lead lfcsp_vq cp-32-2 AD5750-2bcpz-rl7 0.1 0 to 2.5 2.5 ?40c to +105c 32-lead lfcsp_vq cp-32-2 1 z = rohs compliant part. 3.25 3.10 sq 2.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom s eating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq 0.60 max 0.60 max 0.25 min 05-23-2012-a top view exposed pad bottom view
ad5750/ad5750-1/AD5750-2 data sheet rev. e | page 34 of 36 notes
data sheet ad5750/ad5750 - 1/ad5750 - 2 rev. e | page 35 of 36 notes
ad5750/ad5750-1/AD5750-2 data sheet rev. e | page 36 of 36 notes ?2009C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07268-0-6/12(e)

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